Abstract
PreviewThis International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently.
The contents given in this specifications are as follows:
a) System bus interface signal provisions;
b) Bus operations and transfer protocol for each bus operation;
c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system;
d) Fault detection function using parity check and duplex configuration for control signals.
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Status: PublishedPublication date: 1999-12
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Edition: 1Number of pages: 81
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- ICS :
- 35.160 Microprocessor systems
Buy this standard
| Format | Language | |
|---|---|---|
| std 1 208 | ||
| std 2 208 | Paper |
- CHF208
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